With the rapid development of modern technology, electronic devices are becoming more and more intelligent, especially the intellectualization of mobile phones is significantly prominent. Currently, the design trend of the mobile phone screen is Incell (in-cell touch)+full screen. However, due to the presence of the front camera and handset, the design of the screen digging (notch design) is inevitable, thus resulting in an irregular screen panel. Once adopting the notch design, the notch design will lead to unsmooth alignment of gate lines in the notch areas. Accordingly, it leads to a larger frame width for the notch areas of the screen, and to a fault of process/yield. Please refer to FIG. 1, which is a diagram of a full screen mobile phone on the market. With the notch design, the panel is divided into a notch area and a non-notch area according to the position of the notch.
The driving circuits of the small and medium size panels can be categorized into a gate driver circuit and a source driver circuit. As shown in FIG. 2, which is a diagram of a driving circuit of a small and medium size panel according to the prior art, the driver IC is bonded to the bottom side of the glass panel and is connected to the host through a flexible circuit board assembly (FPCA) to implement the source driver function. The Gate driver circuit is implemented by a GOA circuit, ie, an array substrate row driving circuit (Gate Driver On Array). It can be simply understood as implementing some of the functions of the Gate Driver on the glass panel. Meanwhile, under normal circumstances, the GOA circuits are placed on the left and right sides of the glass panel respectively, and the GOA circuits are driven by means of interlaced driving (the GOA circuit at the left side drives Gate line1/Gate line3/Gate line5 . . . , and the GOA circuit at the right side drives Gate line2/Gate line4/Gate line6 . . . ).
In the Incell+Notch panel, the existence of the notch results in the Gate line detour in the notch area. The frame width of the notch area of the screen panel will be influenced. As shown in FIG. 3, which shows a scan line interlaced driving design scheme of two notch areas according to the prior art. The Gate line design for the notch area according prior art have two categories: 1, as shown in the left side of FIG. 3, the Gate line detour for the notch area is directly implemented in the GE layer (Gate layer). The disadvantage of this method is that the length of the line in the GE layer is too long and it is prone to line injury/damage. 2, as shown in the right side of FIG. 3, the perforation to the SD layer (Source layer) is used for the Gate line detour in the notch area. The disadvantage of this method is that the perforation to the SD layer is required, which will results in process complication/yield reduction.